MAX5856的技术资料

AV_DD, DV_DD, PV_DDto AGND, DGND, PGND..................-0.3V to +4V
DA7–DA0, DB7-DB0, CW, REN, PLLF, PLLEN to AGND,
     DGND, PGND........................................................-0.3V to +4V
IDE to AGND, DGND, PGND.........................-0.3V to (DV_DD+ 0.3V)
CLKXN, CLKXP to PGND.............................................-0.3V to +4V
OUTP_, OUTN_ to AGND...........................-1.25V to (AV_DD+ 0.3V)
CLK, LOCK to DGND...................................-0.3V to (DV_DD+ 0.3V)  
REFR, REFO to AGND..................................-0.3V to (AV_DD+ 0.3V)
AGND to DGND, DGND to PGND,
AGND to PGND...................................................-0.3V to +0.3V
Maximum Current into Any Pin
(excluding power supplies)...............................................±50mA
Continuous Power Dissipation (T_A= +70°C)
48-Pin TQFP-EP (derate 36.2mW/°C above +70°C).........2.899W
Operating Temperature Range............................-40°C to +85°C
Storage Temperature Range..............................-65°C to +150°C
Junction Temperature.......................................................+150°C
Lead Temperature (soldering, 10s)..................................+300°C


Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The MAX5856A dual, 8-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5856A integrates two 8-bit DAC cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (PLL) clock multiplier, and a 1.24V reference. The MAX5856A sup- ports single-ended and differential modes of operation. The MAX5856A dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of  -1.0V to +1.25V.

The 4x/2x/1x programmable interpolation filters feature excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and the clock speeds of the digital interface. The PLL multiplier generates all internal synchronized high-speed clock signals for interpolating filter operation and DAC core conversion. The internal PLL helps minimize system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5856A to be updated on a single 8-bit bus.

The MAX5856A features digital control of channel gain matching to within ±0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The on-chip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications.

The MAX5856A features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1µA. The MAX5856A is packaged in a 48-pin TQFP with exposed paddle (EP) for enhanced thermal dissipation and is specified for the extended (-40°C to +85°C) operating temperature range.